1. Field of the Invention
The present invention relates to a method for forming silicide on a semiconductor wafer, and more particularly, to a method for forming silicide while simultaneously preventing impurities in a doped silicon layer from outgassing during rapid thermal processing steps.
2. Description of the Prior Art
Metal-oxide-semiconductor (MOS) transistors are important components of semiconductor circuits, and the electrical performance of the gate in the MOS transistor is an important issue that effects the quality of MOS transistors. The prior art gate typically includes a doped polysilicon layer or a doped amorphous silicon layer used as the main conductive layer, and a silicide layer stacked on the conductive layer. The silicide layer provides a good ohmic contact to the devices of the MOS transistor, thus reducing sheet resistance and enhancing the operational speed of the MOS transistor.
Please refer to FIG. 1 to FIG. 3. FIG. 1 to FIG. 3 are schematic diagrams of the method for forming silicide 28 on a semiconductor wafer 10 according to the prior art. As shown in FIG. 1, the semiconductor wafer 10 includes a substrate 12. The substrate 12 shown in FIG. 1 is used to form a MOS transistor, and the silicide 28 is a portion of the gate electrode of the MOS transistor. The substrate 12 includes a gate oxide 14, a doped polysilicon layer 16 stacked on the gate oxide 14, and two spacers 18 formed adjacent to the gate 17. In the prior art method, a thin film deposition process is performed to form a cobalt layer 22 on the substrate 12 and the gate 17. A titanium nitride (TiN) layer 24 is then deposited on the cobalt layer 22 using a sputtering method.
As shown in FIG. 2, a rapid thermal processing (RTP) step is performed, the process temperature between 720.degree. C. and 760.degree. C., to make portions of the cobalt layer 22 react with silicon inside the doped polysilicon layer 16 and inside the silicon substrate 12 around the gate 17 so as to form a transitional silicide 26. The transitional silicide is a cobalt-rich silicide, such as CoSi or Co.sub.2 Si. The titanium nitride layer 24 and the portions of the cobalt layer 22 that have not reacted with the silicon are then removed.
Another rapid thermal processing step is then performed, the process temperature between 830.degree. C. and 870.degree. C., to make the transitional silicide 26 react with portions of the doped silicon layer 16 and the silicon substrate 12 so as to form the cobalt silicide (CoSi.sub.2) 28 that is much more stable and which has a low resistance. Finally, a chemical vapor deposition (CVD) process is performed to form a dielectric layer 29 of silicon dioxide, which covers the gate 17, as shown in FIG. 3.
Because there is no barrier layer or passivation layer covering the transitional silicide 26 during the second rapid thermal processing step, impurities, such as arsenic or phosphorus, in the doped polysilicon layer 16 will outgass during the rapid thermal processing step. This results in an impurity dosage in the doped polysilicon layer 16 that is less than the predetermined dosage, and affects the conductive capability and electrical performance of the gate electrode. In addition, a portion of the impurities outgassing from the doped polysilicon layer adhere to the surface of the chamber of the rapid thermal processing machine, which can contaminate or even harm the machine.